StrongArm Comparator

Circuit Description:

The StrongArm Latch, like others latches, excels at storing and maintaining a state. Unique to the StrongArm latch topology, however, is that it consumes zero static power and provides rail-to-rail outputs. In the modern age with the need for power efficient and fast electronics, the StrongArm Latch plays an important role in a lot of electronics and can often find their use in comparator applications.

In operation, the StrongArm Comparator consists of three defined phases: Reset, Amplification, and Regeneration. The reset stage has the latch undergo a pre-charge that sets the voltage at the output and intermediate nodes at a defined voltage (VDD) through the capacitances at those nodes. 

During the amplification phase, transistors connected to the comparator input signals are allowed to sink current through the tail current source, discharging the intermediate pre-charged nodes. Due to differences in the magnitude of the two input signals, one leg of the comparator will discharge faster than the other.

Finally, during the Regeneration phase, the cross coupled PMOS devices near top of the structure provide positive feedback and enforce a high differential voltage at the output nodes (one output falls to zero while the other rises to VDD), which has a polarity dictated according to the whichever input leg discharged enough during the amplification phase to activate the cross-coupled pair.

Figure 1: StrongArm Comparator Schematic

Device	Width/Length (um)
S1	(0.5/0.15)
S2	(0.5/0.15)
S3	(0.5/0.15)
S4	(0.5/0.15)
M1	(5/0.15)
M2	(5/0.15)
M3	(0.5/0.15)
M4	(0.5/0.15)
M5	(2/0.15)
M6	(1/0.15)
M7_1	(1.5/0.15)
M7_2	(1.5/0.15)
M8	(1/0.15)
M9	(1/0.15)
M10	(2/0.15)
M11	(1/0.15)

Table 1: Device Sizes

Figure 2: StrongArm Comparator Layout (All Layers)

Figure 3: StrongArm Comparator Layout: Poly Layer

Figure 4: StrongArm Comparator Layout: Metal Layer

Figure 5: Pre-Extraction Results (Response Time – 141.49ps, Avg. Power Consumption – 42.64uW)

 In Figure 5 we can see some of the metrics of the StrongArm Comparator design. The response time (the time it takes for the rising output to latch to half of VDD after a differential input is applied) is 141.49ps, while average power consumption during comparator operating is measured at 42.64uW.

Figure 6: Post Extraction Results (Response Time – 286.37ps, Avg. Power Consumption – 73.22uW)

In Figure 6 we can see the effects of layout and parasitic extraction in the waveforms given. The response time of the comparator has increased by nearly double to 286.37ps, while average power consumption has increased to 73.22uW as well. We can attribute this degradation to parasitic capacitance and resistance that are a result of layout.

Figure 7: Post Extraction Response Time (Purple) alongside Pre-Extraction Response Time (Red)

In Figure 7, we can better see the response time degradation due to parasitic extraction and layout by placing the ‘pre’ and ‘post’ layout waveforms next to each other on the same graph axis.